1. Field of the Invention
Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer.
2. Description of the Related Art
In semiconductor devices, unit elements such as a plurality of transistors, resistors and capacitors may be formed on a semiconductor substrate, and may be electrically connected to constitute a semiconductor integrated circuit. The unit elements constituting the semiconductor device may be connected to one another via interconnects.
In the conventional art, the metal interconnects of semiconductor devices developed to perform higher speed operation are not formed within the semiconductor integrated circuits, but unit elements are electrically connected using a separately formed interposer.
FIG. 1 shows a construction of a semiconductor device using a conventional interposer.
Referring to FIG. 1, a semiconductor device 10 may have an interposer 11 and a semiconductor integrated circuit 12. The interposer 11 may have a semiconductor substrate 14, a metal interconnect 16, and/or an InterLayer Dielectric (ILD) layer 18. The semiconductor substrate 14 may be used to fix the metal interconnect 16 of the interposer 11, and may be used to couple the metal interconnect 16 with the semiconductor integrated circuit 12. The metal interconnect 16 may electrically connect the unit elements of the semiconductor integrated circuit 12 via contacts 19. The metal interconnect 16 may be insulated from the semiconductor substrate 14 using the ILD layer 18.
The ILD layer 18 may generally be composed of an insulating material such as SiO2. A dielectric constant ∈ of such an insulating material is greater than that of air. Therefore, an internal parasitic capacitance increased due to the ILD layer 18 makes a total capacitance C large, so that a response speed τ desired for signal transfer of the semiconductor device may be slower. That is, τ is increased because τ=R*C, where R is resistance. Thus, the reaction speed of overall operation of the semiconductor device may be slower.
In the case of a multi-chip package in which several semiconductor chips are connected as a single semiconductor device, a capacitance loading between the metal interconnects that connect the semiconductor chips may become an issue.
FIG. 2 illustrates a relation of connecting respective chips in a conventional multi-chip package.
FIG. 2A illustrates a multi-chip package in which two semiconductor chips are connected in parallel with each other, FIG. 2B illustrates a multi-chip package upon which at least two semiconductor chips are stacked, and FIG. 2C illustrates a multi-chip package in which at least two semiconductor chips are stacked and in parallel with one another.
In a multi-chip package, if semiconductor chips are connected by metal interconnects on or in a substrate as shown in FIG. 2, the response speed of the semiconductor device may be slower because of the greater capacitance loading between the interconnects. The capacitance loading problem caused by the metal interconnects may impede fabrication of integrated circuits operating at higher speed.
Moreover, as shown in FIG. 2, when semiconductor chips are connected via metal interconnects on the substrates, an area occupied by the multi-chip package may be enlarged, which may increase manufacturing costs of the semiconductor devices.
A multi-chip package may be constructed using an interposer. However, a dielectric constant of the ILD layer within the interposer may be large enough to still involve the capacitance loading problem caused by the insulating layer.